The present invention relates to a manufacturing technology of a semiconductor device, particularly to a technology effective when applied to the manufacture of the gate electrode of a first MISFET and the gate electrode of a second MISFET by different steps.
In Japanese Unexamined Patent Publication No. 2004-40041, disclosed is a technology of forming, over one semiconductor substrate, both a low-voltage transistor which operates at a low voltage and a flash memory which operates at a high voltage and has a two-layer electrode structure called ETOX.
Described specifically, both a field oxide film for element isolation and a protection oxide film for ion implantation are formed over a semiconductor substrate in order to form a low-voltage transistor region and a flash memory region. After the formation, by lithography, of a first resist pattern in which only the low-voltage transistor region is opened, ion implantation for controlling the threshold voltage of the low-voltage transistor is carried out. The first resist pattern is removed and lithography is then performed again to form a second resist pattern in which only the flash memory region is opened. The protection oxide film is removed only from the flash memory region by etching.
After removal of the second resist pattern, a gate oxide film of the flash memory is formed and then a first-level gate electrode material is formed over the flash memory region. The protection oxide film is removed by etching from the low voltage transistor region, whereby a gate oxide film of the low voltage transistor is formed. Simultaneously with this, an interlayer insulating film of the flash memory is formed. After formation of a second-level gate electrode material, lithography and etching are performed to form a gate electrode of the low-voltage transistor and a gate electrode of the flash memory.